For overcoming the current leakage problem encountered in an advanced manufacturing process, a design with multi-domain-voltage islands becomes a mainstream in the art. As such a design requires frequent power on/off transitions, a power-detecting module is generally provided for each domain of the multi-domain-voltage islands to facilitate normal operation of each domain in the power-on state. The power-detecting module is principally used for detecting the power supply state.
Generally speaking, power switches for multi-domain-voltage islands include a header type and a footer type of switches. A header-type power switch consists of PMOS transistors, while the footer-type power switch consists of NMOS transistors. Furthermore, the header-type power switch is coupled to a power source and a virtual power source, while the footer-type power switch is coupled to ground and virtual ground.
For example, in the header-type power switch, when a voltage from a power supply passes through the PMOS transistor switch so that the virtual power increases to a level of 90% or above the power voltage (Vcc), the power-detecting module will generate and output a first power-ready signal to an integrated circuit for normal operations of all elements in the integrated circuit. On the other hand, in the footer-type power switch, when a voltage from a power supply passes through the NMOS transistor switch so that the virtual ground decreases to a level of 10% or below the power voltage (Vcc), the power-detecting module will generate and output a second power-ready signal to an integrated circuit to indicate the suspension of power voltage (Vcc) from the power supply.
In order for the power-detecting module to accurately measure the power voltage (Vcc) from the power supply, a level-detecting circuit included in the power-detecting module is used for detecting the voltage level from the power supply. A general level-detecting circuit is implemented with an analog circuit, and is thus disadvantageous in some aspects, e.g. large layout area, high DC current consumption, high IC design cost, etc. Alternatively, the level-detecting circuit can be implemented with a digital circuit. In the digital circuitry, equivalent resistance and capacitance in the power supply are calculated first and then used for calculating an RC time constant. Afterwards, a digital counter measures the charge/discharge time after the power on/off operation so as to opportunely generate the first/second power-ready signal.
A further attempt is to use a Schmitt trigger which is simple in structure and exhibits a hysteresis transfer function as the level-detecting circuit.
Please refer to FIG. 1 which schematically illustrates a conventional Schmitt trigger as disclosed in U.S. Pat. No. 3,984,703. The Schmitt trigger includes three NMOS transistors 14, 18 and 19 and three PMOS transistors 13, 16 and 17. The Schmitt trigger has an input end (in) coupled to gates of the NMOS transistors 14 and 19 and the PMOS transistors 13 and 16. The source of the PMOS transistor 16 is coupled to a voltage source Vcc and the drain is coupled to a node 21. The node 21 is further coupled to the source of the PMOS transistor 13 which has the drain coupled to an output end (out). The output end (out) is coupled to the drain of the NMOS transistor 14 which has the source coupled to a node 22. The node 22 is further coupled to the drain of the NMOS transistor 19 which has the source grounded. Furthermore, the source of the PMOS transistor 17 is coupled to the node 21, the gate is coupled to the output end (out), and the drain is coupled to ground. On the other hand, the source of the NMOS transistor 18 is coupled to the node 22, the gate is coupled to the output end (out), and the drain is coupled to the voltage source Vcc.
Please refer to FIG. 2 which is a plot showing a hysteresis transfer function of the Schmitt trigger of FIG. 1. Assuming that the voltage Vcc is 10V, the threshold voltage of the NMOS transistors is a positive value Vthn, and the threshold voltage of the PMOS transistors is a negative value Vthp, then:    (I) If the input has a voltage lying between 0 and Vthn, the PMOS transistors 13 and 16 and the NMOS transistor 18 are turned on while the PMOS transistor 17 and the NMOS transistors 14 and 19 are turned off; meanwhile, the output end has a voltage equal to Vcc, and the node 22 has a voltage equal to (Vcc−Vthn);    (II) When the voltage at the input end rises and lies in a range between Vthn and Vcc/2+Vthn, the PMOS transistors 13 and 16 and the NMOS transistors 18 and 19 are turned on while the PMOS transistor 17 and the NMOS transistor 14 are turned off; meanwhile, the output end has a voltage equal to Vcc, and the node 22 has a voltage equal to (Vcc/2);    (III) When the voltage at the input end further rises and lies in a range between Vcc/2+Vthn and Vcc, the PMOS transistor 17 and the NMOS transistors 14 and 19 are turned on while the PMOS transistors 13 and 16 and the NMOS transistor 18 are turned off; meanwhile, the output end has a 0 voltage, and the node 21 has a voltage equal to −Vthp;    (IV) If the input has a voltage lying between Vcc and Vcc+Vthp, the NMOS transistors 14 and 19 and the PMOS transistor 17 are turned on while the PMOS transistors 16 and 13 and the NMOS transistor 18 are turned off; meanwhile, the output end has a 0 voltage, and the node 21 has a voltage equal to −Vthp;    (V) When the voltage at the input end falls and lies in a range between Vcc+Vthp and Vcc/2+Vthp, the NMOS transistors 14 and 19 and the PMOS transistors 16 and 17 are turned on while the PMOS transistors 13 and the NMOS transistor 18 are turned off; meanwhile, the output end has a 0 voltage, and the node 21 has a voltage equal to Vcc/2; and    (VI) When the voltage at the input end further falls and lies in a range between Vcc/2+Vthp and 0, the PMOS transistors 13 and 16 and the NMOS transistor 18 are turned on while the PMOS transistors 17 and the NMOS transistors 14 and 19 are turned off; meanwhile, the output end has a voltage equal to Vcc, and the node 22 has a voltage equal to Vcc−Vthn.
It is understood from FIG. 2 that when the input voltage increases from 0 to Vcc, the trip point V+ at the output end is Vcc/2+Vthn; and when the input voltage decreases from Vcc to 0, the trip point V− at the output end is Vcc/2+Vthp. Since the difference between the two trip points V+ and V− is defined as a hysteresis level, it is realized that the trip point V− is around 0.3 Vcc and the trip point V+ is around 0.7 Vcc. Unfortunately, for using a Schmitt trigger as the level-detecting circuit of the power-detecting module, it is required that the trip points V− and V+ are at least low to 0.1 Vcc and up to 0.9 Vcc.
U.S. Pat. No. 6,870,413 discloses a Schmitt trigger circuit with adjustable trip point voltages, as illustrated in FIG. 3. The Schmitt trigger includes a NOT gate 180, an inverter stage 120, two NMOS transistor control circuits, two PMOS transistor control circuits, two NMOS transistors T0 and T1, and two PMOS transistors T4 and T5. The Schmitt trigger has an input end (VIN) coupled to gates of the NMOS transistors T0 and T1 and the PMOS transistors T4 and T5. The source of the PMOS transistor T4 is coupled to the voltage source Vcc and the drain is coupled to a node 140. The node 140 is further coupled to the source of the PMOS transistor T5 which has the drain coupled to a node 130. The node 130 is coupled to the drain of the NMOS transistor T1 which has the source coupled to a node 150. The node 150 is coupled to the drain of the NMOS transistor T0 which has the source coupled to ground Vss. Furthermore, the node 130 is coupled to the input end of the inverter stage 120 which has an output end serving as the output end (VOUT) of the Schmitt trigger.
Furthermore, the Schmitt trigger includes a first NMOS transistor control circuit 160 including NMOS transistors T11 and T12, wherein the drain of the NMOS transistor T12 is coupled to the voltage source Vcc and the gate and the source are coupled to the node 130 and the drain of the NMOS transistor T11, respectively. The gate of the NMOS transistor T11 is coupled to an output end /VCCSEL of the NOT gate 180 and the source is coupled to the node 150. The Schmitt trigger further includes a second NMOS transistor control circuit 165 including NMOS transistors T13 and T14, wherein the drain of the NMOS transistor T14 is coupled to the voltage source Vcc and the gate and source are coupled to the node 130 and the drain of the NMOS transistor T13. The gate of the NMOS transistor T13 is coupled to a selection end VCCSEL of the NOT gate 180 and the source is coupled to the node 150.
Furthermore, the Schmitt trigger includes a first PMOS transistor control circuit 170 including PMOS transistors T9 and T10, wherein the drain of the PMOS transistor T10 is coupled to ground Vss and the gate and the source are coupled to the node 130 and the drain of the PMOS transistor T9, respectively. The gate of the PMOS transistor T9 is coupled to the selection end VCCSEL of the NOT gate 180 and the source is coupled to the node 140. The Schmitt trigger further includes a second PMOS transistor control circuit 175 including PMOS transistors T7 and T8, wherein the drain of the PMOS transistor T8 is coupled to ground Vss and the gate and the source are coupled to the node 130 and the drain of the PMOS transistor T7, respectively. The gate of the PMOS transistor T7 is coupled to the output end /VCCSEL of the NOT gate 180 and the source is coupled to the node 140.
In the Schmitt trigger circuitry, the first NMOS transistor control circuit 160 and the second NMOS transistor control circuit 165, which exhibit different conductivity parameters, and the first and second PMOS transistor control circuits 170 and 175 also with different conductivity parameters are provided. By selectively enabling the first and second NMOS transistor control circuits 160 and 165 or the first and second PMOS transistor control circuits 170 and 175 through the selection end, the trip point of the Schmitt trigger may vary with the signal from the control end so as to impart two hysteresis transfer functions to the Schmitt trigger, as shown in FIG. 4A and FIG. 4B.
In another prior art, U.S. Pat. No. 6,441,663, SOI CMOS Schmitt trigger circuits with controllable hysteresis are proposed. Please refer to FIG. 5. The Schmitt trigger includes 5 NMOS transistors N1, N2, N3, N4 and N5, and 5 PMOS transistors P1, P2, P3, P4 and P5. In order to eliminate a so-called body effect of the transistors, the bodies of the NMOS transistors N1, N2 and N3 are coupled to ground, while the bodies of the PMOS transistors P1, P2 and P3 are coupled to voltage source Vdd. On the other hand, the bodies of the NMOS transistors N4 and N5 are coupled to the sources of the NMOS transistors N4 and N5, respectively, while the bodies of the PMOS transistors P4 and P5 are coupled to the sources of the PMOS transistors P4 and P5, respectively.
The Schmitt trigger further includes an input$ end VIN coupled to the gates of the NMOS transistors N1, N2 and N3 and the PMOS transistors P1, P2 and P3. Meanwhile, the source of the PMOS transistor P1 is coupled to the voltage source Vcc and the drain is coupled to a node “a”. The node “a” is coupled to the source of the PMOS transistor P2 which has the drain coupled to a node “b”. The node “b” is coupled to the source of the PMOS transistor P3 which has the drain coupled to an output end VOUT. The output end VOUT is coupled to the drain of the NMOS transistor N3 which has the source coupled to a node “c”. The node “c” is coupled to the drain of the NMOS transistor N2 which has the source coupled to a node “d”. The node “d” is coupled to the drain of the NMOS transistor N1 which has the source coupled to ground.
In the circuitry, the PMOS transistors P4 and P5 and the NMOS transistors N4 and N5 may function as feedback FETs. The Schmitt trigger utilizes two tires of feedback FETs to control two trip points, i.e. for both V+ and V−. The source of the PMOS transistor P5 is coupled to the node “b” and the gate and drain are coupled to the output end VOUT and ground, respectively. The source of the PMOS transistor P4 is coupled to the node “a” and the gate and drain are coupled to the source of the PMOS transistor P5 and ground, respectively. On the other hand, the source of the NMOS transistor N5 is coupled to the node “c” and the gate and drain are coupled to the output end VOUT and the voltage source Vcc, respectively. The source of the NMOS transistor N4 is coupled to the node “d” and the gate and drain are coupled to the source of the NMOS transistor N5 and the voltage source Vcc, respectively.
As the interconnection among the feedback FETs P4, P5, N4 and N5, while being turned on, is likely to result in voltage variation at the node “b” or “c”, inaccurate trip points V+ and V− of the Schmitt trigger may thus occur. In other words, due to the connection of the gate of the PMOS transistor P4 to the source of the PMOS transistor P5, the voltage variation would have influence on the trip point V− at the node “b” when the PMOS transistors P4 and P5 are turned on. Likewise, due to the connection of the gate of the NMOS transistor N4 to the source of the NMOS transistor N5, the voltage variation would have influence on the trip point V+ at the node “c” when the NMOS transistors N4 and N5 are turned on. As a result, such a Schmitt trigger is not suitable to be a level detection circuit used in a power-detecting module.